Energy Efficient High Performance Computing Working Group Links and Events
 
 
 

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A list of GreenIT Conferences is avaiable at: GreenIT Conferences.org


November 2017

Event: SC17
Date/Time: November 12-17, 2017
Location: Denver, Colorado
Website: http://sc17.supercomputing.org/

Event: 5th International Workshop on Energy Efficient SuperComputing (E2SC) Held in conjunction with SC'17
Date/Time: November 13, 2017
Location: Denver, Colorado
Note: See below for detailed information
Website:http://hpc.pnl.gov/conf/e2sc/2017/


January 2018

Event: Call for Papers
Subject: 6th International Workshop on Power-Efficient GPU and Many-core Computing (Held in conjunction with HiPEAC 2018)
Date/Time: January 22, 2018
Location: Manchester, UK
Note: See below for detailed information
Website: http://lpgpu.org/wp/pegpum-2018/
Papers: Submission deadline November 20, 2017


March 2018

Event: Call for Papers
Subject: Topic A1: Power-efficient and Sustainable Computing
Date/Time: March 19-23, 2018
Location: Dresden, GERMANY
Note: See below for detailed information
Website: https://www.date-conference.com/call-for-papers#The-Conference
               https://www.date-conference.com/group/tpc/members/2018/A1
Papers: Submission deadline September 10, 2017

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Event Details

Event: Call for Papers

Event: 5th International Workshop on Energy Efficient SuperComputing (E2SC) Held in conjunction with SC'17
Date/Time: November 13, 2017
Location: Denver, Colorado
Website:http://hpc.pnl.gov/conf/e2sc/2017/

With Exascale systems on the horizon, we will be ushering in an era with power and energy consumption as a key concern for scalable computing. To achieve viable high performance, a combination of evolutionary and revolutionary methods is required with a stronger integration among hardware features, system software and applications. Equally important are the capabilities for fine-grained spatial and temporal measurement and control to facilitate energy efficient computing across all layers. Current approaches for energy efficient computing rely heavily on power efficient hardware in isolation. However, it is pivotal for hardware to expose mechanisms for energy efficiency to optimize power and energy consumption for various workloads and to reduce data motion, a major component of energy use. At the same time, high fidelity measurement techniques, typically ignored in data-center level measurement, are of high importance
for scalable and energy efficient inter-play at different layers of application, system software and hardware.

This workshop seeks to address the important energy efficiency aspects in the HPC community that have not been previously addressed by aspects covered in the data center or cloud computing communities. Emphasis is given to an application's view related to significant energy efficiency improvements as well as to the required hardware/software stack that must include necessary power and performance measurement, and analysis harnesses. 

Current tools are often limited by hardware capabilities and their lack of information about the characteristics of a given workload/application. In the same manner, hardware techniques, like dynamic voltage frequency scaling, are often limited by their granularity (very coarse power management) or by their scope (a very limited system view). More rapid realization of energy savings
will require significant increases in measurement resolution and optimization techniques.  Moreover, the interplay between performance, power and reliability add another layer of complexity to this already difficult group of challenges.

Workshop Focus:

We encourage submissions in the following areas:

  • Tools for power and energy analysis with different granularities and  scope from hardware (e.g., component, core, node, rack, system) or  software views (e.g., threads, tasks, processes, etc.) or both.
  • Tools and techniques for measurement, analysis, and modeling of thermal  effects at different granularities (e.g., component, core, node, rack,  system) for large-scale systems.
  • Techniques that enable power and energy optimizations at different  scale levels for HPC systems.
  • Integration of power-aware technologies in applications and throughout  the software stack of HPC systems.
  • Characterization of current state-of-the-art HPC systems and  applications in terms of power.
  • Disruptive infrastructure hardware technologies for energy-efficient  supercomputing.
  • Analysis of future technologies that will provide improved energy consumption and management on future HPC systems.

Organizing Committee:

General Chairs:           

  • Kirk Cameron, Virginia Tech, USA
  • Adolfy Hoisie, PNNL, USA
  • David Lowenthal, University of Arizona, USA
  • Dimitrios S. Nikolopoulos,Queen's University of Belfast,UK
  • Sudha Yalamanchili, Georgia Institute of Technology, USA

Program Co-Chairs:   

  • Jim Larus, Sandia, PNNL,
  • USAKevin J. Barker, PNNL, USA

Publicity Chair:

  • Andres Marquez, PNNL, USA

European Liaison:

  • Michele Weiland, EPCC, UK

Publication Chair:

  • Joseph Manzano, PNNL, USA

Panel Chair:

  • Barbara Chapman, SUNY/BNL, USA

Important Dates:

  • Paper Submission:    8th September 2017
  • Paper Notification:     27th September 2017
  • Final Papers Due:     4th October 2017

Submission Guidelines:

Papers should not exceed ten single-space pages (including figures, tables and references) using a 10-point on 8.5x11-inch pages (US Letter). 

Submissions will be judged on correctness, originality, technical strength, significance, presentation quality and appropriateness.

Submitted papers should not have appeared in or should not be under consideration for another venue.

A full peer-review processes will be followed with each paper being reviewed by at least 3 members of the program committee.

Submissions will be made through EasyChair https://easychair.org/conferences/?conf=e2sc0
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Event: Call for Papers
Subject: 6th International Workshop on Power-Efficient GPU and Many-core Computing (Held in conjunction with HiPEAC 2018)
Date/Time: January 22, 2018
Location: Manchester, UK
Website: http://lpgpu.org/wp/pegpum-2018/
Papers: Submission deadline November 20, 2017

SCOPE

The recent success of advanced mobile platforms coincides with the rising challenge of ensuring a long battery life, and accompanies a larger trend away from increasing processor clock speeds in favor of increasing parallelism. That high performance computing (HPC) is also strongly motivated in this area, as witnessed by the recent Green500 List project, illustrates the timeliness and ubiquity of topics relating to low-power computing. In the last years we have seen the introduction of new computing platforms that include multicore CPUs, manycore GPUs and application-specific accelerators, some of them specially addressing low-power mobile applications. The design of applications, architectures, and supporting programming tools for low-power parallel computing systems is an open and very active research field. This workshop in conjunction with HiPEAC18 on low-power computing intends to foster dialogue and interaction among researchers from academia and industry addressing contemporary challenges in low-power parallel software and hardware design.

SUBMISSIONS

Authors are invited to submit original and unpublished contributions as 6-page papers in IEEE double column format to be considered as regular papers or 2-page papers to be considered as extended abstracts.

Important Dates

  • Paper submission deadline: 20 November, 2017
  • Acceptance notification: 15 December, 2017

Please log in to easychair to submit your paper: https://easychair.org/conferences/?conf=pegpum2018

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Event: Call for Papers
Subject: Topic A1: Power-efficient and Sustainable Computing
Date/Time: March 19-23, 2018
Location: Dresden, GERMANY
Papers: Submission deadline September 10, 2017
Website: https://www.date-conference.com/call-for-papers#The-Conference
               https://www.date-conference.com/group/tpc/members/2018/A1

DATE 2018, will take place from 19 to 23 March, 2018, at the International Congress Center in Dresden, Germany.

The conference addresses all aspects of research into technologies for electronic and embedded systems engineering. The conference has a dedicated track for Application Design (Track A). This track is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies.

We invite you to submit papers to this track and particularly to topic A1 - Power-efficient and Sustainable Computing. This topic focuses on application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). New highlights of this year are emerging topics in power-efficient computing, such as machine learning based approaches for power and energy management, as well as emerging neuromorphic architectures for highly energy efficient computing systems.

Main themes of interest (but not limited to) of A1 topic:
------------------------------------------------------

  • Emerging trends in energy-efficiency, like neuromorphic architectures and approximate computing
  • Emerging communication or computing systems (e.g., power-efficient machine learning accelerators)
  • Software architectures for energy-efficient computing
  • Virtualization
  • Energy-efficient memory
  • Low-power processors
  • Heterogeneous computing
  • Resource management techniques
  • Innovative data-center management strategies
  • SW/OS-level implementations in real systems and data centers
  • Energy-efficient big data management
  • Data centers powered by renewable energy sources and data centers in smart grids.

Topic Chair: Muhammad Shafique, Technische Universität Wien, AT
Topic Co-Chair: Baris Aksanli, San Diego State University, US

Topic Members:
Luca Benini, Università di Bologna, IT
Hai (Helen) Li, Duke University, US
Umit Ogras, Arizona State University, US
Alexandre Valentian, CEA-Leti, FR

Please note:
----------------------
SUBMISSION DEADLINE: Sunday, 10 September, 2017.
All papers have to be submitted electronically via the conference web page (see www.date-conference.com/submission-instructions).

 
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