Event: Call for Papers
Subject: 6th International Workshop on Power-Efficient GPU and Many-core Computing  (Held in conjunction with HiPEAC 2018)
Date/Time: January 22, 2018
Location: Manchester, UK
Website: http://lpgpu.org/wp/pegpum-2018/
Papers: Submission deadline November 20, 2017

SCOPE

The recent success of advanced mobile platforms coincides with the rising challenge of ensuring a long battery life, and accompanies a larger trend away from increasing processor clock speeds in favor of increasing parallelism. That high performance computing (HPC) is also strongly motivated in this area, as witnessed by the recent Green500 List project, illustrates the timeliness and ubiquity of topics relating to low-power computing. In the last years we have seen the introduction of new computing platforms that include multicore CPUs, manycore GPUs and application-specific accelerators, some of them specially addressing low-power mobile applications. The design of applications, architectures, and supporting programming tools for low-power parallel computing systems is an open and very active research field. This workshop in conjunction with HiPEAC18 on low-power computing intends to foster dialogue and interaction among researchers from academia and industry addressing contemporary challenges in low-power parallel software and hardware design.

SUBMISSIONS

Authors are invited to submit original and unpublished contributions as 6-page papers in IEEE double column format to be considered as regular papers or 2-page papers to be considered as extended abstracts.

Important Dates

• Paper submission deadline: 20 November, 2017
• Acceptance notification: 15 December, 2017

Please log in to easychair to submit your paper: https://easychair.org/conferences/?conf=pegpum2018

Event: Call for Papers
Subject: Topic A1: Power-efficient and Sustainable Computing
Date/Time: March 19-23, 2018
Location: Dresden, GERMANY
Papers: Submission deadline September 10, 2017
Website: https://www.date-conference.com/call-for-papers#The-Conference
               https://www.date-conference.com/group/tpc/members/2018/A1

DATE 2018, will take place from 19 to 23 March, 2018, at the International Congress Center in Dresden, Germany.

The conference addresses all aspects of research into technologies for electronic and embedded systems engineering. The conference has a dedicated track for Application Design (Track A). This track is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies.

We invite you to submit papers to this track and particularly to topic A1 - Power-efficient and Sustainable Computing. This topic focuses on application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). New highlights of this year are emerging topics in power-efficient computing, such as machine learning based approaches for power and energy management, as well as emerging neuromorphic architectures for highly energy efficient computing systems.

Main themes of interest (but not limited to) of A1 topic:

• Emerging trends in energy-efficiency, like neuromorphic architectures and approximate computing
• Emerging communication or computing systems (e.g., power-efficient machine learning accelerators)
• Software architectures for energy-efficient computing
• Virtualization
• Energy-efficient memory
• Low-power processors
• Heterogeneous computing
• Resource management techniques
• Innovative data-center management strategies
• SW/OS-level implementations in real systems and data centers
• Energy-efficient big data management
• Data centers powered by renewable energy sources and data centers in smart grids.

Topic Chair: Muhammad Shafique, Technische Universität Wien, AT
Topic Co-Chair: Baris Aksanli, San Diego State University, US

Topic Members:
Luca Benini, Università di Bologna, IT
Hai (Helen) Li, Duke University, US
Umit Ogras, Arizona State University, US
Alexandre Valentian, CEA-Leti, FR

Important Dates

SUBMISSION DEADLINE: Sunday, 10 September, 2017.
All papers have to be submitted electronically via the conference web page (see www.date-conference.com/submission-instructions).

Event: Call for Papers
Subject: The 14th International Workshop on High-Performance, Power Aware Computing (HPPAC'18)
              (Held in conjunction the 32nd IEEE International Parallel and Distributed Processing Symposium (IPDPS 2018))
Date/Time: May 21, 2018
Location: Vancouver, British Columbia CANADA (JW Marriott Parq Vancouver Hotel)
Website: The 14th International Workshop on High-Performance, Power Aware Computing (HPPAC'18)
               IPDPS - IEEE International Parallel & Distributed Processing Symposium
Papers: Submission deadline January 29, 2018

SCOPE

Power and energy are now recognized as first-order constraints in high-performance computing. Optimizing performance under power and energy bounds requires coordination across not only the software stack (compilers, operating and runtime systems, job schedulers) but also coordination with cooling systems and outwards to electrical suppliers. As we continue to move towards exascale and extreme scale computing, understanding how power translates to performance becomes an increasingly critical problem.

The purpose of this workshop is to provide a forum where cutting-edge research in the above topic can be shared with others in the community. We welcome submissions addressing power aware computing issues. All papers will be subject to single-blind peer review, and the quality of standard papers is expected to be high.

Topics of particular interest include (but are not limited to):

• Performance optimization under node, job, cluster and site power bounds
• Power/performance tradeoffs across accelerators, processors and DRAM
• Cooling/performance tradeoffs
• Translating budgetary bounds into power and energy bounds
• Power-efficient system design, from computer center to silicon
• Effects of compiler optimizations on application power and energy efficiency
• Power- and energy-aware job schedulers, runtime systems and operating systems
• Models of power and performance, from processors and components to computer centers
• Evaluations of hardware power and energy controls
• Applications specific power and energy optimization

Submission Guidelines

Papers should not exceed ten single-spaced pages for long papers (including figures, tables and references) or four single-spaced pages for short papers (not including the references) using 12-point font on 8.5x11- inch pages.
Submissions will be judged on correctness, originality, technical strength, significance, presentation quality, and relevance.

Submitted papers should not have appeared in or be under consideration for another venue. A full peer-review process will be followed with each paper being reviewed by at least three members of the program committee.

Submissions should follow the IEEE Conference Proceedings templates found at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html

Camera-ready copy will need to conform to IPDPS guidelines; these will be announced during author notification.

Program Co-Chairs:    

• Shuaiwen Leon Song, Pacific Northwest National Lab and College of William & Mary
• Natalie Bates, Energy Efficient HPC Working Group
• Ang Li, Pacific Northwest National Lab

Publicity Chair:

• Joseph Manzano, Pacific Northwest National Lab

Important dates

Paper Submission (for both short and long papers): January 29th, 2018
Paper Notification: February 28th, 2018
Final Paper Due: March 7th, 2018