Energy Efficient High Performance Computing Working Group:
Sustainably supporting science through committed community action


Responsibilities: Sets EE HPC WG technical and administrative strategy, policies and procedures. Creates and maintains effective Technical Teams and EE HPC WG activities.

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Natalie Bates, Co-Chair

Natalie Bates


Natalie has led the Energy Efficient High Performance Computing Working Group (EE HPC WG) since its inception in 2010. Natalie has been the technical and executive leader for this ‘open source’ working group that disseminates best practices, shares information (peer to peer exchange), and takes collective action. Prior to leading the EE HPC WG, Natalie's career spanned twenty years with Intel Corporation where she was a senior manager of highly complex programs taking new products to market, delivering multi-component and multi-partner platforms, and negotiating strategic technical industry initiatives.  She is a strong advocate and effective agent for organizational change, transition and process improvement.  Her broader interest is to influence human’s impact on the planet by promoting sustainability and leveraging her extensive experience with computing and collaboration.  Natalie has a BA in Sociology from Reed College and studied Electrical Engineering at Sacramento State University, California.

Anna Maria Bailey, Co-Chair

Anna Maria Bailey


Anna Maria is Lawrence Livermore National Laboratory’s (LLNL) HPC Chief Engineer.  She holds a B.S. in Electrical Engineering from Cal Poly, San Luis Obispo and is registered with the California Board for Professional Engineers and Land Surveyors. She has more than 30 years of experience in multiple engineering roles at LLNL, notably serving as the design/construction manager for LLNL’s HPC Center, which houses some of the world’s most powerful supercomputers. In addition, she led the effort to earn LEED certification for two HPC facilities and is currently overseeing the planning of an Exascale facility modernization project to prepare for unprecedented Exascale facility infrastructure challenges. She also serves as the co-chair of the Energy Efficient HPC Working Group (EE HPC WG). Their mission is to reduce expenditure and curb environmental impact through increased efficiencies in HPC centers by encouraging the community to lead in energy efficiency as they do in computing performance.

Torsten Wilde, Conferences Co-Lead

Torsten Wilde


Torsten (Ph.D.) is a system architect for HPC system monitoring and system power and energy management at Hewlett Packard Enterprise (HPE). His research activities are related to high volume, high frequency data collection and analytics for improved IT operations as well as dynamic power management. Torsten has published more than two dozen research papers mainly related to power and energy usage and improvement in High Performance Computing. Torsten received his MSc in parallel and scientific computation from the University of Liverpool, UK, and his MSc in Computer Engineering from the University of Applied Sciences in Berlin, Germany. He received his Ph.D. in computer science from the Technical University of Munich, Germany, in 2018.

Siddhartha Jana, Conferences Co-Lead

Siddartha Jana


Sid (Ph.D.) is a research scientist at Intel Corporation and the conferences co-lead within the EE HPC WG (Energy Efficient HPC Working Group). He holds a doctorate from the University of Houston in energy efficiency and distributed memory programming models. At Intel, his research projects are driven towards leveraging hardware features to explore energy efficiency within the HPC software stack. His other research interests include programming models, High Performance Computing, compiler design and analyses, runtime systems, communication libraries, and distributed computing. As part of his research, he has collaborated with a number of organizations across academia, government, and the industry including Total, Oak Ridge National Laboratory, Technische University, Dresden, Intel, Los Alamos National Laboratory and Cray Inc. With his two hats on - Intel and EE HPC WG, Sid is actively collaborating on HPC PowerStack, a community-wide effort to design a unified HPC system stack that will facilitate building system-wide power efficiency solutions for future large-scale machines

James H. Laros III, Systems Co-Lead

James Laros


James is a Distinguished Member of Technical staff at Sandia National Laboratories. Over his more than 30-year career to date, James has served the United States of America in a number of capacities beginning with four years active duty in the United States Air Force followed by a year in the Air National Guard. James continued his service as a civilian as part of the Strategic Defense Initiative program in Colorado working as a Systems Analyst. James began working at Sandia in 1995 where he has focused on various technical disciplines related to High Performance Computing (HPC) including Hierarchical Mass Storage, file-systems, systems management and systems software, Reliability Availability and Serviceability (RAS) systems and light-weight kernel operating systems. Over the past ten years James has focused on technical leadership in the area of HPC platform architecture. James currently leads many programs including: Vanguard Advanced Architecture Prototype program, Astra Chief Architect and project lead, the Alliance for Extreme Scale Computing (ACES) Crossroads lead architect and deputy program manager, and the Advanced Architecture Testbed program lead. James has won numerous awards including three R&D100 awards.

John Shalf, Systems Co-Lead

David Shalf


John is Department Head for Computer Science Lawrence Berkeley National Laboratory, and recently was deputy director of Hardware Technology for the DOE Exascale Computing Project. Shalf is a coauthor of over 80 publications in the field of parallel computing software and HPC technology, including three best papers and the widely cited report “The Landscape of Parallel Computing Research: A View from Berkeley” (with David Patterson and others). He also coauthored the 2008 “ExaScale Software Study: Software Challenges in Extreme Scale Systems,” which set the Defense Advanced Research Project Agency’s (DARPA’s) information technology research investment strategy. Prior to coming to Berkeley Laboratory, John worked at the National Center for Supercomputing Applications and the Max Planck Institute for Gravitation Physics/Albert Einstein Institute (AEI) where he was was co-creator of the Cactus Computational Toolkit.

David Grant, Infrastructure Co-Lead

David Grant


David graduated from the University of Tennessee in 2003 with a B.S. in Mechanical Engineering. He has been at the Oak Ridge National Laboratory (ORNL) since 2009 and is a senior technical staff member.  While at ORNL he has been involved with the design, construction, and operation of the mechanical systems supporting ORNL's 80,000SF+ of data centers which house the Summit and Frontier High Performance Computer Systems among others. He is currently a co-chair of the Energy Efficient HPC Working Group Infrastructure sub-team and is a corresponding member of the ASHRAE TC9.9. David is a registered Professional Engineer with the State of Tennessee and is a Certified Energy Manager (CEM - from the Association of Energy Engineers (AEE)) and a Data Center Energy Practitioner – Specialist (DCEP - from the Department of Energy (DOE)). 

David Martinez, Infrastructure Co-Lead

David Martinez


Dave is an Engineering Program/Project Lead and has worked in the Sandia National Laboratories Corporate Computing Facilities (CCF) for 35+ years. David is the subject matter expert for SNL’s data center operations and design due to his in-depth understanding and experience with HVAC, controls, and mechanical and electrical systems. David is frequently consulted by internal and external agencies for design review and his innovative approach to data center management and energy efficient operations and designs. SNL has received numerous energy efficiency awards as a result of these efforts. During his tenure, David has seen the data center operations move from about 20,000 sq. ft. to over 100,000 sq. ft. comprised of 4 unique data center environments which includes a Leed gold HPC data center.