January 2019

 

Event: HIP3ES 2019 (Held in conjunction with HiPEAC 2019)

Subject: International Workshop on High Performance Energy Efficient Embedded Systems (7th Edition)

Date/Time: Tuesday January 22nd, 2019

Location: Valencia, Spain

 

As the microelectronics industry is moving towards many-core processors, new opportunities and new challenges raise for high performance computing in the embedded domain. HIP3ES aims at providing a high-quality forum to bring together researchers and practitioners to present new results and ongoing work on all aspects related to high-performance and energy efficient embedded systems. We welcome theoretical and experimental papers, academic and industrial research, rock-solid and preliminary results, experience reports on existing techniques/technologies and wild new ideas, with the goal to build a lively workshop, to initiate collaborations and to inspire new advances.

 

Topics of interest include, but are not limited to:

 

• Low Power High Performance Embedded Systems

• Resource Management in Many-core systems

• Runtime support for Many-core systems

• Virtualization in embedded systems

• Language and development tool-chains for High Performance Embedded Systems
  
  

 

Event: Call For Papers

Subject: CFP: JSA Special Issue on Energy-Efficient Many-Core Embedded Systems and Architectures

Date/Time: Submission of manuscripts: 30 January 2019

 

SCOPE OF THE SPECIAL ISSUE

 

In the last decades, a significant boost in many-core embedded systems performance has occurred thanks to rapid technology scaling and increasing exploitation of parallel processing architectures. With increasing number of cores integrated on a chip, on-chip communication is becoming the power and performance bottleneck in current and future many-core Systems-on-a-Chip (SoCs). A variety of on-chip interconnects, such as dedicated buses, Network-on-Chip (NoC), hybrid bus-NoC, etc., have been proposed to meet the performance and design productivity requirements of the complex on-chip communication infrastructure. The trend to merge multiple functions on a single chip poses significant challenges to the design and integration of such systems. Energy efficiency is obviously very important for the multitude of edge devices used in the emerging Internet-of-Things (IoT) era. This Special Issue focuses on energy-efficient many-core embedded systems and architectures. The topics of interest include, but not limited to:

 

• Energy-efficient reconfigurable many-core architectures
• Novel many-core architectures for low power embedded systems
• Low-power many-core architectures for digital signal processing
• NoC architectures and applications NoC interconnection simulators and emulators
• NoC support for memory and cache access
• NoC design and simulation methodologies and tools
• NoC for FPGA and structured ASIC

• Heterogeneous multicore programming for low power many-core architectures
• Neuromorphic architectures Authors of papers presented at NoCArc 2018, the 11th ACM/IEEE International Workshop on Network on Chip Architectures, are invited to submit extended journal version of their papers to the SI. Other authors may also submit original manuscripts that fit within the scope of the SI.

 

SUBMISSION DETAILS

 

General information for submitting papers to JSA can be found at https://www.journals.elsevier.com/journal-of-systems-architecture (please note the “Guide for Authors” link). Submissions to this Special Issue (SI) should be made using Elsevier’s editorial system at the journal website (https://www.evise.com/profile/api/navigate/JSA), under the "Submit Your Paper" link). Please select the “SI:NoCArc18” option as the type of the paper during the submission process.

 

JSA has adopted the Virtual Special Issues model to speed up the publication process, where an SI paper is published in a regular issue as soon as it is accepted. Therefore, authors are encouraged to submit papers early, and need not wait until the submission deadline.

 

IMPORTANT DATES

 

• Submission of manuscripts: 30 January 2019
• Notification to authors: 30 March 2019
• Final versions due: 30 June 2019

 

GUEST EDITORS

 

Karthigai Kumar

Karpagam College of Engineering, Coimbatore, India

 

Kun-Chih (Jimmy) Chen

National Sun Yat-sen University, Taiwan

 

Maurizio Palesi

University of Catania, Italy

 

Midia Reshadi

Science and Research Branch of Islamic Azad University, Iran

 

May 2019

 

Event: Call For Papers (Workshop On Energy-Secure System Architectures)

Subject: In Conjunction With The 12TH IEEE International Symposium On Hardware Oriented Security And Trust (HOST 2019)

Date/Time: May 9-10th, 2019

Location: McLean, VA

Website:www.essa-workshop.org

 

Papers

 

Extended Abstracts must be in English and up to 4 pages.

Accepted papers will be presented at the workshop and included in the workshop report.

Selected papers presented in the workshop will be invited to submit revised (updated) versions to a peer-reviewed special issue of IEEE Security and Privacy

 

Topics Of Interest (but not limited to)

 

• Power, noise and thermal management solutions for modern multi-core platforms: with a focus on reliability and security challenges.

• Verification and design for verification of system-level power, noise and thermal managers: predeployment safeguards against security breaches.

• Reliability and security holes exposed by power/thermal management protocols: specific examples of attack scenarios.

• Security-aware dynamic power management: software-hardware architectural concepts.

• Use of machine learning/deep learning (ML/DL) principles in safeguarding against energy attacks in processors, server systems and data-centers.

• Architectural implications of and system software support for energy-secure systems.

• Security and reliability issues in emerging low power processor and memory technology.

• Resilience and security challenges of ultra-low power cognitive IoT systems Energy-secure artificial intelligence (AI) systems.

• Metrics for quantifying energy-security of computing systems.

 

Overview

 

The "power wall" has forced chip and system architects to design with smaller margins between nominal and worst-case operating points. Dynamic power, voltage noise and thermal management control loops have already become an integral part of chip and system design. New research papers in “wear out” and general reliability management have recently been published.

 

These new generation management protocols have, however, opened up other sources of concern: e.g. control loop stability and robustness of the management protocols. The potential security holes exposed by the integrated control loops and system safety issues triggered by potential violations of power or thermal limits are other areas of concern. Also, side channel attack scenarios enabled by modulated power profiles have been documented in prior research.

 

We seek to motivate the research community into adopting a holistic approach to mitigating the power wall and the concomitant reliability-security wall. We have coined the term "Energy-Secure System Architectures" to cover the range of research being pursued within industry and academia in order to ensure robust and secure functionality, while meeting the energy-related constraints of the "green computing" era. This segmented workshop offering, composed of lectures provided by experts in the areas of power/thermal management, reliability and security, provides a comprehensive view of the hardware and software aspects of Energy-Secure System Architectures

 

Important Dates

 

Submission Deadline: March 1st, 2019

Acceptance Decision: March 15th, 2019

Final Submission: April 5th, 2019

Presentation Slides: April 26th, 2019

 

 

Technical Program Committee

 

Saibal Mukhopadhyay, Georgia Tech University

Pradip Bose, IBM Research

Alper Buyuktosunoglu, IBM Research

Augusto Vega, IBM Research

Francisco J. Cazorla, Barcelona Supercomputing Center

Simha Sethumadhavan, Columbia University

Moinuddin Qureshi, Georgia Tech University

Edward Suh, Cornell University

Sanu Matthew, Intel Corporation

 

Organizing Commitee

 

Saibal Mukhopadhyay, Georgia Tech University

Pradip Bose, IBM T.J.Watson Research Center

 

Contact

 

Saibal Mukhopadhyay - saibal@ece.gatech.edu

Pradip Bose - pbose@us.ibm.com

 

More info at www.essa-workshop.org

 

 

July 2019

 

Event: OPTIM'2019 - Int. Workshop on Optimization of Energy Efficient HPC & Distributed Systems

Date/Time: July 15 – July 19, 2019

Location: Dublin, Ireland

Submission Deadline: March 11th, 2019

Website:http://hpcs2019.cisedu.info/2-conference/workshops/workshop02-optim

 

Scope And Objectives

 

Energy efficiency optimization has gradually become one fundamental constraint and requisite in the design of High Performance Computing

(HPC) and Distributed Systems, comprehending several prominent research domains embracing the processor architectures (homogeneous/heterogeneous many-core GPPs), the processing accelerators and co-processors (e.g., APUs, GPUs, FPGAs, etc.), the distributed infrastructures (clusters, grids, data centers, etc.), the distributed platforms (application models, framework runtimes and virtual machines), and the underlying network and communication subsystem. Moreover, even in the embedded domain, saving energy in battery-supplied devices is established as a fundamental issue in mobile, hand-held and wireless applications and in most pervasive systems.

 

Accordingly, due to the often imposed thermal, power and energy constraints, an effective minimization and optimization of the energy

consumption surpasses the obvious economic impact of the energy cost, since it also directly affects other aspects of the overall infrastructure with a significant influence on its viability, including the power supply and its distribution, cooling mechanisms (cost and space overhead) and management techniques, etc.

 

These new challenges require innovative and effective solutions to attain an effective optimization and/or minimization of the power

consumption in HPC and distributed systems, including energy-efficient architectures, scheduling and mapping algorithms, load-balancing and

scalability studies, and communication protocols.

 

The goal of this workshop is to bring together active researchers who are interested in prevailing issues and prominent challenges related to

optimizing computing systems power consumption, energy efficient systems, power-aware distributed systems, and green computing.

 

The OPTIM workshop topics of interest include (but are not limited to) the following:

 

• Computer architecture trends for energy efficiency: Heterogeneous parallel processing architectures; ISA diversity and morphable structures; run-time reconfiguration/adaptation and dynamic scalability; CPU accelerator co-design (GPUs, APUs, FPGAs, etc.); approximate computing techniques and architectures.

 

• Energy/power management and control: Run-time power/energy monitoring and sensing; heat/power/energy models; Dynamic Voltage and Frequency Scaling (DVFS) and power/clock gating strategies; performance vs. power/energy scaling and management.

 

• Energy-aware large scale distributed systems: energy-efficient grids, clouds and data centers; exascale computing systems; energy-aware virtualization techniques for energy efficiency; energy-aware frameworks; virtual machines and network infrastructure management.

 

• Energy-aware communication: energy-efficient models, protocols and and network infrastructure management. routing algorithms applied in the physical (PHY), data-link (MAC), network (IP), transport (TCP/UDP) and middleware layers above; energy-efficient cross-layer protocols; energy trade offs between communication and computation; energy-efficient network services and operations.

 

• Tools and algorithms: Programing languages, compilers and models for energy-aware computing; profiling and simulation tools for heat/power/energy estimation; power- and thermal-aware scheduling, mapping and task/thread migration policies for energy efficiency; energy-aware resource management; operating system support and energy management tools.

 

• Green Computing: models, methodologies and paradigms; sustainable computing; management and balance between performance, reliability and energy consumption; standardization and benchmarking for energy-aware systems; integration with smart grids. Both theoretical papers and papers describing systems implementations and real-world practical experiences will be welcome.

 

Instructions For Paper Submittal

 

You are invited to submit original and unpublished research works on above and other topics related to optimization issues in energy

efficient high performance and distributed computing systems.  Submitted papers must not have been published or simultaneously submitted elsewhere.

 

Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and email addresses.  Indicate

clearly the corresponding author and include up to 6 keywords from the above list of topics and an abstract of no more than 400 words.  The

full manuscript should be at most 8 pages using the two-column format. Additional pages will be charged additional fee.  Short papers (up to 4

pages), poster papers and posters (please refer to HPCS’2019 webpage for the posters submission details) will also be accepted for submission. In case of multiple authors, an indication of which author(s) is responsible for correspondence must be indicated. Please include page numbers on all submissions to make it easier for reviewers to provide helpful comments.

 

Submit your manuscript to the Workshop submission site: https://easychair.org/conferences/?conf=optim2019

 

Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews.  Papers will be

selected based on their originality, relevance, significance, technical clarity and presentation, and references.  Submission implies the

willingness of at least one of the authors to register and present the paper, if accepted.  At least one of the authors of each accepted paper will have to register and attend the HPCS’2019 conference to present the paper at the Workshop.

 

Proceedings

 

Accepted papers will be published in the conference proceedings. Instructions for final manuscript format and requirements will be posted

on the HPCS’2019 web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time

of the conference. The proceedings is projected to be included in the IEEE Digital Library and indexed in major indexing services accordingly.

 

Important Dates

 

• Abstract Submission (EasyChair): March 4, 2019
• Paper Submissions (EasyChair):   March 11, 2019
• Acceptance Notification:                April 3, 2019
• Camera Ready Papers:                April 19, 2019
• Registration Due:                          April 19, 2019
• Conference Dates:                       July 15 - 19, 2019

 

Workshop Organizers

 

• Nuno Roma, INESC-ID, Instituto Superior Técnico, Univ. Lisboa (Nuno.Roma@inesc-id.pt)

• Luís Veiga, INESC-ID, Instituto Superior Técnico, Univ. Lisboa (Luis.Veiga@inesc-id.pt)